Record-Breaking Energy Efficiency for SRAM

Researchers from Holst Centre, imec and and the Katholieke Universiteit Leuven (K.U. Leuven) have demonstrated the world’s most energy efficient 64kbit SRAM operating at 90MHz. At just 2.65pJ per access, the new SRAM consumes 5-20 times less energy than the previous state of the art. It opens the door to a range of new energy-harvesting applications in body-area networks (BANs) for healthcare and sensor networks for smart buildings.

BANs promise heath monitoring systems that can keep an eye on your vital signs around the clock without disrupting normal daily life. The ultimate goal is systems that draw energy from their environment. But this “energy harvesting” requires sensors that consume very little power.

“For a typical wireless processor today, accessing the node’s memory accounts for about 75% of the energy it uses. So by making SRAM more efficient, you can make a big difference to the nodes overall energy usage – possibly as much as a factor of 3,” said Jos Huisken, principal scientist at Holst Centre specializing in ultra-low-power digital signal processing.

The Holst Centre/imec/K.U. Leuven team achieved the record-breaking figure of 2.65pJ per access (read or write cycle) by taking a fresh look at the way an SRAM is designed. Instead of prioritizing clock speed and silicon area, the group optimized their design for energy efficiency and variability resilience. To do this, the group used an innovative SRAM architecture with a low-energy charge-limited sequential sense amplifier and a novel mimicked negative bit-line technique. The design was then realized in a test chip fabricated in 65-nm LP CMOS.

According to Vibhu Sharma, a doctorate student at K.U Leuven who developed the test chip, this patented energy-saving technology could be used in many other applications. “Our test chip operates at 90MHz. Our group has also shown that the techniques behind it can also be applied at higher frequencies so could be used for applications such as cell phones and embedded processors that have higher memory performance requirements than BAN nodes,” he explained.

The record-breaking SRAM was announced at the European Solid-State Circuits Conference (ESSCIRC), held in Helsinki, Finland in September 2011. Work is currently ongoing to prepare the low-power techniques for industrialization, for example through integration into an SRAM compiler. The group is also looking for industrial partners to support the transfer to litho-optimized SRAM cells.