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Imec, KULeuven and AIST Report New Process that Paves the Way Toward Increased Mobility of Meyond 10nm MOS Devices

Tensile-strained GeSn MOSFET devices on Si developed using solid phase epitaxy

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By: DAVID SAVASTANO

Contributing Editor, Coatings World and Ink World

KULeuven, imec and AIST have developed a solid phase epitaxy process to integrate germanium tin (GeSn) metal-oxide semiconductor field-effect transistor (MOSFET) devices on silicon. For the first time, operation of depletion-mode junctionless GeSn pMOSFET on silicon was demonstrated, an important step toward achieving tensile strain in MOSFET devices, and increasing their mobility.

To improve performance in next-generation scaled complementary metal-oxide semiconductor (CMOS) devices, researchers are exploring the integration of novel materials with superior electron mobility. This includes GeSn, a promising semiconductor candidate as channel material, due to its superior physical properties. GeSn enables increased switching speed of MOSFET devices and can be used in fast optical communication. While most prototype GeSn channel MOSFETs are fabricated on Ge substrates, silicon integration is preferred for CMOS compatibility.

Researchers from KULeuven, imec and AIST developed a solid phase epitaxy process, achieving ultrathin (~10nm) single-crystalline GeSn layers on silicon substrates showing tensile strain, attractive for strain engineering of Ge channels. Furthermore, it reduces the difference between the direct and indirect band transition, resulting in acquisition of a direct band gap group IV material. Lastly, due to its non-equilibrium deposition conditions, the new method enables the development of GeSn with high Sn concentrations .

By decreasing the channel thickness with reactive ion etching (RIE) from ~30 to ~10 nm, the researchers improved the on/off ratio by more than one order of magnitude. Additionally, hole depletion in the ultrathin (~10 nm) GeSn layers on silicon resulted in good transfer characteristics with an on/off ratio of 84. In the future, research will focus on optimizing the GeSn MOSFET on silicon devices to further increase the channel mobility.

More details on these results will be presented at the Solid State Devices and Materials (SSDM) conference in Fukuoka, Japan on Sept. 25, and will be published in Applied Physics Express 2013.

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