Applied Materials Announces Breakthrough in Chip Wiring

Applied Materials, Inc. unveiled a new way to engineer the wiring of advanced logic chips that enables scaling to the 3nm node and beyond.

While size reduction benefits transistor performance, the opposite is true in the interconnect wiring: smaller wires have greater electrical resistance which reduces performance and increases power consumption. Without a materials engineering breakthrough, interconnect via resistance would increase by a factor of 10 from the 7nm node to the 3nm node, negating the benefits of transistor scaling.

Applied Materials has developed a new materials engineering solution called the Endura Copper Barrier Seed IMS. It is an Integrated Materials Solution that combines seven different process technologies in one system under high vacuum: ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology. The combination replaces conformal ALD with selective ALD, eliminating a high-resistivity barrier at the via interface. The solution also includes copper reflow technology that enables void free gap fill in narrow features.

Electrical resistance at the via contact interface is reduced by up to 50%, improving chip performance and power consumption, and enabling logic scaling to continue to 3nm and beyond.

“A smartphone chip has tens of billions of copper interconnects, and wiring already consumes a third of the chip’s power,” said Prabu Raja, SVP and GM of the Semiconductor Products Group at Applied Materials. “Integrating multiple process technologies in vacuum allows us to reengineer materials and structures so that consumers can have more capable devices and longer battery life. This unique, integrated solution is designed to accelerate the performance, power and area-cost roadmaps of our customers.”

The Endura Copper Barrier Seed IMS system is now being used by leading foundry-logic customers worldwide.